1. Field of the Invention
The present invention relates to a semiconductor element (or semiconductor device) and a process for the production of the same. Particularly, the present invention relates to a semiconductor element and a process for the production of such an element which contains an electrode forming a Schottky junction such as a field effect transistor (FET) (for example a GaAsMESFET (metal-semiconductor field effect transistor) or an HEMT (high electron mobility transistor)), a Schottky barrier diode and so on.
2. Description of the Related Art
GaAsMESFET
A GaAs FET containing a Schottky gate (hereinafter, referred to as "GaAsMESFET") has been used as a semiconductor element, for supplying a high output in a high frequency band, such as a high frequency amplifying element, due to its good high frequency characteristics (especially, its high speed response).
Generally, the GaAsMESFET has the problem of a low drain withstand voltage and a low gate withstand voltage because of the effects of a high density surface defect state in an active layer surface of a GaAs substrate and an electric field concentration in the active layer immediately below a gate electrode. It is necessarily desired for a high output GaAsMESFET to improve its drain withstand voltage and the gate withstand voltage for the purpose of the improvement of its output power limit and also its reliability.
FIGS. 34 to 36 generally show a sequence of a process for the production of a GaAsMESFET (71) wherein the transistor is shown as its cross sectional view. in the process, a positive-type (hereinafter referred to as "p-type") impurity is implanted into a surface layer of a semi-insulation GaAs substrate (40) to form a p-type active layer (41), then a negative-type o (hereinafter referred to as "n-type") impurity is implanted to form a n-type active layer (42), further an n-type impurity is implanted in a source region and a drain region to form an n.sup.+ -type active layer (43) on each side of the n-type active layer (see FIG. 34), and then an ohmic metal is placed on the n.sup.+ -type active layers (43) to form a source electrode (44) and a drain electrode (45) (see FIG. 35). Then, a gate electrode (47) is provided in a recess (46) prepared by etching a portion of the n-type active layer (42) (see FIG. 36).
Thus, an electric field strength near the drain electrode (45) is lowered by providing the n.sup.+ -type active layers (43) in the source region and the drain region, whereby the drain withstand voltage is improved. In addition, the electric field concentration near the gate electrode (47) and the drain electrode (45) is decentralized so as to lower the electric field strength, so that the drain withstand voltage and the gate withstand voltage are improved.
However, the withstand voltages of the element having a structure as shown in FIG. 36 are not sufficiently low. Therefore, in respect of the GaAsMESFET, suppression of tunneling, and improvement of a barrier height, improvement of the gate withstand voltage in various manners, have been attempted. For example, the decentralization of the electric field concentration in the active layer and lowering of a leakage current as well as the improvement of the withstand voltage with a LDD (Lightly Doped Drain) structure and a multi-step recess structure have been studied and practically carried out. Concrete improvements are, for example, (1) the improvement of the barrier height by properly selecting a metal for the gate electrode; (2) the improvement of the gate withstand voltage by a specific treatment of a GaAs substrate interface; and (3) the improvement of the gate withstand voltage by providing a buffer layer on the active layer of a GaAs substrate.
FIG. 37 shows a GaAsMESFET (72) having the LDD structure in its sectional view, in which an n'-type layer (48) having a lower carrier concentration than an n.sup.+ -type active layer (43) is formed between an n-type active layer (42) carrying a gate electrode (47) and each n.sup.+ -type active layer (43) carrying a source electrode (44) and a drain electrode (45). Thus, an excess-strength of an electric field at an interface between the n.sup.+ -type active layer (43) and n-type active layer (42) is suppressed so that the drain withstand voltage and the source withstand voltage are improved.
FIG. 38 shows a GaAsMESFET (73) in its cross sectional view which has a buffer layer provided on a GaAs substrate (51). As the buffer layer, one undoped surface layer (53) is formed on an active layer (52) which is on the GaAs substrate (51).
The GaAsMESFET (73) as shown in FIG. 38 is produced by the following procedures: The undoped surface layer (53) is formed on the active layer (52) which is on the GaAs substrate (51), and an n-type resistive layer having a lower resistance (54) is formed on the undoped surface layer. Then, an ohmic source electrode (56) and an ohmic drain electrode (57) are formed on the resistive layer (54) before an oxide film (55) of SiO.sub.2 is formed between the source electrode (56) and the drain electrode (57). Thereafter, by dry etching with masking using a patterned resist film (not shown), an opening is formed through the oxide film (55) and a recess having an sufficient depth for embedding a gate electrode is also formed. Next, the oxide film (55) is side-etched to give a predetermined recess length and the recess is etched to a predetermined depth. Finally, a gate electrode (58) is provided which forms a Schottky junction by deposition of a metal such as Al/Ti/WSi and lifting off unnecessary metal and the resist film. The gate electrode (58) is formed on the active layer (52) and extends through the undoped surface layer (53) in the example of FIG. 38. However, the gate electrode (58) may also be formed on the undoped surface layer (53).
In the GaAsMESFET (73) having the undoped surface layer (53), no current limitation occurs due to channel narrowing between the gate region and the drain region or between the gate region and source region, whereby almost the same effect as in the LDD structure or the multi-step recess structure is obtained. In addition, a surface effect based on an interface state is buffered by the undoped surface layer (53) so that the gate withstand voltage is improved.
However, the prior art GaAsMESFET as described above having the LDD structure or the multi-step recess structure is complicated in its structure, and thus a process for the production of such an element, of course, becomes complicated, production control is difficult, reliability of the element is not enough and commercial application is also difficult. Similarly, production of the GaAsMESFET (73) as shown in FIG. 38 requires the steps of the formation of the undoped surface layer, the dry etching, for example by the RIE (reactive ion etching) process and the side etching which are complicated. It is difficult to control such a process, so the cost of production of such an element is high. Further, other elements besides those described above are also complicated in structure and their production also requires complicated steps.
Among the prior art elements, the GaAsMESFET as shown in FIG. 38 seems to provide the highest output and the highest efficiency. In such a prior art element, the active layer (52), the undoped surface layer (53) and the n-type lower resistance layer (54) as described above are formed by the epitaxial growth method. When the epitaxial growth method is applied, the undoped surface layer (53) which has a high resistance necessarily lies between the ohmic electrode (the source electrode (56) or the drain electrode (57)) and the active layer (52), which means the increase of a parasitic resistor which lies in series with a channel.
The following principles are generally applied to an output of an FET (field effect transistor). FIG. 39 shows a graph indicating its static characteristic curve of a drain current (I.sub.d) as a function of a voltage (V.sub.ds) between a source electrode and a drain electrode and also a load curve (I). When the FET is operated as a class "A" amplifier, a maximum output power (Po.sub.max) can be calculated according to the following equation (1): EQU Po.sub.max =I.sub.max .times.(BV.sub.ds -V.sub.knee)/8 (1)
wherein I.sub.max is a maximum current, V.sub.knee is a knee voltage (which is a voltage at a bend), and BV.sub.ds is a breakdown voltage each of which are obtained from the graph of FIG. 39.
According to the above equation (1), in order to increase the maximum output power (Po.sub.max), I.sub.max and/or BV.sub.ds must be increased and/or the knee voltage (V.sub.knee) must be decreased. Generally, it is necessary to lower a resistance of an element in order to increase the maximum current (I.sub.max) or decrease the knee voltage (V.sub.knee). On the other hand, to obtain a high withstand voltage due to the increased breakdown voltage (BV.sub.ds) requires a higher resistance. Thus, these parameters cannot be determined independently.
In the GaAsMESFET (73) as shown in FIG. 38, the insertion of the undoped surface layer (53) makes the breakdown voltage (BV.sub.ds) increased, resulting in the higher withstand voltage. However, a resistor component which lies in series with the channel is increased as described above and thus the maximum current (I.sub.max) is decreased and the knee voltage (V.sub.knee) is increased. Therefore, the maximum power (Po.sub.max) cannot be effectively increased. In addition, in order to apply the element to a portable electric equipment, the maximum current (I.sub.max) must be increased and the knee voltage (V.sub.knee) must be decreased so that the element can be operated at a lower voltage with a smaller power consumption. Thus, the GaAsMESFET element having such a structure as shown in FIG. 38 which has the higher withstand voltage does not satisfy the requirements as described above. And, in addition to the problems as to the maximum output power described above, problems similar to those occur as to the efficiency of the element.